Both manufacturers and purchasers of integrated circuits are concerned about the causes and rates of electrical failures of such circuits. In the manufacturing and design context, by determining the reasons for time-zero failures of integrated circuits, the manufacturer can identify and implement effective corrective actions in order to increase the manufacturing yield, thereby reducing manufacturing costs. It is also well known that certain failure mechanisms are time-dependent, such that failures of integrated circuits occur at various rates over the operating life of a given population. Manufacturers of integrated circuits predict the reliability of circuits by way of accelerated testing of samples of the production population; analysis of the failure mechanisms from such accelerated testing allows for mechanism-dependent failure rate prediction, and also allows for identification and verification of reliability-related corrective actions. Purchasers and users of integrated circuits are also interested in the causes of field failures, so that corrective action on the vendor's part may be identified and implemented.
In recent years, modern integrated circuits have been fabricated with multiple layers of metallization. A relatively likely location for both time-zero and later life electrical failures in such circuits is the interconnection between the multiple metallization layers, such interconnection generally made by way of metal-filled vias at selected locations through the insulating layer between metallization levels. The interconnecting metal within the via may be the same metal as in the connected layers; for example, interconnection of aluminum metal lines may be made by aluminum-filled vias therebetween. Alternatively, materials other than that of the metallization layers may make the connection therebetween, examples of such materials including tungsten metal, and tungsten and other metal silicides, for the example of aluminum-based metallization systems. Examples of processes for making such interlevel metallization connection through vias are described in Chen, et al., "Planarized Aluminum Metallization for Sub-0.5 .mu.m CMOS Technology", IEDM Digest of Technical Papers, paper 3.4.1 (IEEE, December 1990), pp. 51-54; Lee, et al., "A Selective CVD Tungsten Local Interconnect Technology", IEDM Digest of Technical Papers, (IEEE, December 1988), pp. 450-53; and Ono, et al., "Development of a Planarized Al-Si Contact Filling Technology", VMIC Conference (IEEE, Jun. 12-13, 1990), pp. 76-81. Other methods for forming such interconnection are also well known.
Conventional failure analysis techniques generally include layer-by-layer "de-processing" of integrated circuit chips, with visual and elemental inspection of the chip prior to the removal of the next layer. Various types of inspection include, of course, visual inspection of the chip, generally by way of optical microscopy or a scanning electron microscope (SEM). Examples of conventional analytical techniques include Auger and EDS (energy dispersal system) spectroscopy, for qualitatively analyzing the chip surface at selected locations; each of these techniques bombard the chip surface with nuclear particles (electrons, etc.), and measure the frequencies of energy emitted from such bombardment, such frequencies indicative of the elements present at the bombarded location.
The layer-by-layer deprocessing of integrated circuit chips, while commonly used to discover many conventional failure mechanisms, is relatively risky, however, as the causes of certain failure types may be removed along with the prior layer. For example, if a failure is due to a contaminant between two layers, and if the etchant used to remove the overlying layer also removes the contaminant, the true cause of the failure may not ever be determined.
In particular, when an open connection within the via between metal layers is suspected as the cause of failure, prior failure analysis techniques have avoided layerwise deprocessing of the integrated circuit chip, specifically to avoid removing of the cause of failure along with the overlying metallization layer. Therefore, prior failure analysis techniques, in inspecting a suspected open-via failure, have relied upon cleaving the circuit through the suspected failing via, followed by SEM or analytical inspection of the cross-sectional view of the via. Unfortunately, this technique does not always result in successful identification of the failure cause. A first reason for this is the difficulty in accurately sectioning an integrated circuit chip through a desired via, especially as via sizes are shrinking to on the order of one micron or less. Furthermore, a thin insulating layer present within the via may cause an electrical open without being of sufficient thickness as to be visible in cross-section. In addition, analytical techniques such as Auger or EDS may have a sufficiently large spot size that the metallization on either side of the open dwarfs any spectral signal from the failure-causing material. As a result, conventional cross-sectional cleaving of suspected failing vias often does not lead to a determination of the cause of failure.
It is therefore an object of this invention to provide a more reliable technique of analyzing the cause of a failing via.
It is another object of this invention to provide such a method which preserves the evidence of the cause of failure.
It is a further object of this invention to provide such a method which exposes sufficient area of many failure causes as to allow identification of the material thereat with conventional analytical equipment.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification, together with the claims.